1. Field of the Invention
The present invention generally relates to methods of forming DRAMs (dynamic random access memory), and more particularly relates to a method of forming synchronous DRAMs (hereinafter called SDRAM), which operates in synchronism with an external clock signal provided from an external source.
2. Description of the Prior Art
There are different types of SDRAMs operating at different frequencies of an external clock signal. One of such SDRAMs is a low-speed one operating at 66 MHz, and another is a high-speed one operating at 125 MHz.
The high-speed SDRAMs include a SDRAM which has two data buses provided for one memory block, and another SDRAM in which one memory block is divided into two memory blocks.
In consecutive data writing, those high-speed SDRAMs receive two data in a sequence, synchronized with an external clock signal, within a time period of two cycles. Those two data are arranged in parallel, and written into the SDRAMs simultaneously within two cycles, which are called a 2 cycle pre-fetch operation. In this manner, those SDRAMs realize a high-speed operation.
In simultaneous data writing of those high-speed SDRAMs, however, data are required to be written into addresses of consecutive column addresses within the same row address. Even if a row address is the same, however, data cannot be simultaneously written into two addresses when their column addresses are not consecutive. Thus, the high-speed SDRAMs require only two cycles for consecutive data writing (simultaneous data writing in actuality) when two addresses have the same row address and consecutive column addresses. However, four cycles become necessary for writing two data when two addresses have the same row address but non-consecutive column addresses.
Nonetheless, the high-speed SDRAMs operate at such a high speed that there is little problem even though consecutive data writing cannot be conducted for addresses having the same row address and non-consequtive column addresses.
On the other hand, the low-speed SDRAMs require consecutive data writing, regardless of column addresses, for two addresses having the same row address in order to make up for their low operating speed. Thus, the low-speed SDRAMs are designed such that consecutive writing operations can be carried out for two column addresses having the same row address.
It might be convenient if there is a single method of manufacturing both the low-speed SDRAMs, which can carry out consecutive writing operations for two addresses having the same row address and arbitrary column addresses, and the high-speed SDRAMs, which can carry out the 2 cycle pre-fetch operations for two addresses having the same row address and consecutive column addresses. Such a method which can readily switch between the manufacturing of the low-speed SDRAMs and the manufacturing of high-speed SDRAMs may bring about a significant advantage in the operations management.
Accordingly, there is a need in the field of SDRAMs for a method of manufacturing both the low-speed SDRAMs and the high-speed SDRAMs which can readily switch from the manufacturing of one type of SDRAMs to the manufacturing of the other type of SDRAMs.